The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming an isolation structure in a semiconductor device.
In a typical shallow trench isolation (STI) process, an oxide material usually fills trenches, and is chemically and mechanically polished using a pad nitride layer as a polishing stop layer. The pad nitride layer is removed so as to form field oxide layers (i.e., isolation structures).
FIG. 1 illustrates a conventional isolation structure. A trench 12 is formed in a substrate 11, and an oxide layer 13 is formed on sidewalls of the trench 12. A nitride-based liner layer 14 is formed on the oxide layer 13. An isolation structure 15 is formed on the nitride-based liner layer 14, while filling the inside of the trench 12.
However, edge portions of the isolation structure 15 are overly etched down to a bottom region of adjacent active regions. In other words, moats M are formed around boundary regions between the edge portions of the isolation structure 15 and the active regions. When a gate oxidation process is performed after the formation of the isolation structure 15, due to the moats M, a gate oxide layer 16 has a profile that is almost vertical and becomes thin around the boundary regions. If the gate oxide layer 16 becomes thin, the gate oxide layer 16 is likely to lose its properties even if external sources such as electric shocks are slightly applied.
FIG. 2A is a micrograph illustrating a gate oxide layer whose thickness decreases in a region where a moat is formed. FIG. 2B is a micrograph illustrating a regularly formed gate oxide layer due to the existence of a nitride-based liner layer.
In particular, FIG. 2A illustrates the gate oxide layer whose thickness decreases in the region where the moat is formed because the nitride-based liner layer is partially oxidized during a subsequent process and removed thereafter. In the region where the moat is formed, the gate oxide layer illustrated in FIG. 2A becomes thinner than that illustrated in FIG. 2B. Reference letter ‘A’ indicates the region where the moat is formed.
The decrease in the thickness of the gate oxide layer in certain regions may result in a limitation in a ramp current stress test (RCST). For instance, reliability of the gate oxide layer may be degraded.
As mentioned above, the nitride-based liner layer is partially oxidized when an oxide material for forming the isolation structure 15 is deposited by a high density plasma process. When the nitride-based liner layer is oxidized, the thickness of the nitride-based liner layer usually changes. During a subsequent cleaning process for removing a pad oxide layer, the oxidized portion of the nitride-based liner layer is overly etched. The over etch of the nitride-based liner layer may induce the formation of moats.